1. Field of the Invention
This invention is related to quality of service (QoS) management for memory transactions in a system.
2. Description of the Related Art
Various types of computing systems generally include a memory system that includes some form of random access memory (RAM). For example, dynamic random access memory (DRAM), such as various forms of double data rate (DDR, DDR2, DDR3, low power versions of the former) synchronous DRAMs (DDR SDRAMs), are currently popular. In some systems, static RAM (SRAM) is used instead of DRAM. The various devices in the system access the memory system using read and write transactions, which include a memory address identifying the memory location(s) accessed by the transaction. Read transactions transfer data from the memory system to the requestor, and write transactions transfer data from the requestor to the memory system. The address is defined in a memory address space that is primarily mapped to the memory system as opposed to peripheral devices such as mass storage devices (e.g. disk drives) and other input/output devices. However, a small portion of the memory address space can be mapped to peripheral devices (“memory-mapped I/O”), typically to access registers within the devices. An I/O address space can be used to access peripheral devices that are not accessible via memory mapped I/O as well.
Computing systems often include numerous devices which require access to memory. Some devices have high memory bandwidth requirements, but are less sensitive to latency. Some devices, e.g. displays, have real-time requirements that involve high bandwidth and predictable latency. Some devices have lower bandwidth requirements but are highly sensitive to latency (e.g. processors such as central processing units (CPUs)).
In order to effectively serve the needs of the disparate devices in a computing system, some memory controllers implement a QoS mechanism in which requestors can rank their transactions in terms of priority and type of service needed. Different requestors can specify their QoS requirements in different ways. However, complications can arise when transactions with higher QoS requirements arrive subsequent to transactions with lower QoS requirements at a particular point in the system.